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  2. The Laterally Diffused MOSFET (LDMOS) is an asymmetric power MOSFET designed for low on-resistance and high blocking voltage. These features are obtained by creating a diffused p -type channel region in a low-doped n -type drain region. The low doping on the drain side results in a large depletion layer with high blocking voltage.
    truenano.com/PSD20/chapter7/ch7_8.htm
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  4. LDMOS topologies (a) low-side: LSD (b) high-side: …

    In this paper, the results of experimental measurements of degradation to failure of different structured SiC power MOSFETs, namely the planar, symmetrical double-trench and asymmetrical trench ...

     
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  10. Design of an LDMOS Transistor Based on the 1 µm …

    A good LDMOS for power/analog applications should have a relatively high breakdown voltage (BV), low on-state resistance (R ON), and a large safe operating area (SOA). It also needs to take into account the characteristics of …

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  11. A new high-side and low-side LDMOST with a selective

  12. A 300-V Ultra-Low-Specific On-Resistance High-Side p-LDMOS …

  13. Optimized 60-V Lateral Dmos Devices for Vlsi Power Applications

  14. Improving breakdown performance for novel LDMOS …

    Apr 1, 2016 · A novel high-voltage device of NFI LDMOS is proposed in this Letter and it is particularly applicable for substrate optimising. A superior performance of BV = 672 V is achieved based on the n + floating islands.

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  15. Improving Specific On-Resistance and Breakdown Voltage in

  16. An Innovated 80V-100V High-Side Side-Isolated N-LDMOS …

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